Storage locking instructions have been used in multi-processor systems to synchronize processes and to insure that only one process has control of a file or a storage area at a given time when more than one processor have requested control of the storage area.
The storage locking instructions used to implement these locks can take many forms, but are all built on the testing and altering of a control word in such a manner that when one processor has access to a block of memory and another processor is trying to access a block of memory with which the control word is associated (e.g., a 4 to 16 word block), it cannot gain control. Some of the terms used to describe these instructions are biased-fetch, test-and-set, increment-and-test, or conditional-replace. They all share one common characteristic in that they access a word, perform a test on that word, and if the test is successful alter the word in such a way that a subsequent processor attempting the same test will fail to ge control.
To accomplish this result, access for the test and the altering of the control word must appear to other users as an indivisible operation. In other words, a second processor must not be allowed to access the control word for testing before the first processor has altered the word. In previous generation machines this was often accomplished by accessing the word and altering it in one storage cycle (a read-alter-write operation), or by locking up the storage unit for two or more cycles, thereby preventing other processors from accessing the unit until the test and modify sequence was complete.
In modern day systems in addition to the shared storage, cache memories are often dedicated to a single processor and are not shared by other processors. With such a system locking instructions become increasingly difficult to implement with reasonable performance characteristics. This is due to the fact that the reference control cell is accessed and modified in the commonly shared memory of the system in order to give the appearance of indivisibility of access, test, and modification. Although, different processors may be running different processes in a multi-processor system, and each of these processors may have a dedicated cache memory which contains a copy of the control cell, some operations must take place in the main storage structure which is common to all of the processors. As processor performance has greatly increased, the main storage system access times have remained relatively constant. This makes locking instructions associated with the slower memories appear to be much slower than other instructions, which can operate out of their dedicated caches without concern for other processors. The slower execution time of these instructions relative to non-locking instructions tends to increasingly dominate program execution times.
U.S. Pat. No. 4,070,706 issued June 24, 1978 to James Scheuneman for a "Parallel Requestor Priority Determination and Requestor Address Matching in a Cache Memory System" and assigned to Unisys Corporation discloses a technique for controlling access to addressed locations of a main storage unit by a plurality of processors each of which had their own cache memory units. The processors each couple their address access requests to an individual register and their separate priority request signals to a priority arbitration device. These priority requests select processors in a predetermined manner. When a processor is selected it compares the address stored in its register with addresses stored in its cache. If a match occurs data is read out of a content addressable location in the cache. If a match does not occur the data is retrieved from the associated address of the main storage unit.
Each processor of the Scheuneman patent is allowed access to the main storage unit only during its own priority period and has to wait for such access until the priority arbitration device signals that higher priority devices had completed their access. Unlike prior devices, however, match determination in the Scheuneman device is complete and, if necessary, the address request is ready for transmission to the main storage unit when priority determination is finished.
The "Memory Block Protection Apparatus" of U.S. Pat. No. 4,099,243 issued July 4, 1978 to Benedict Palumbo, describes block protection of an addressed portion of a memory which allows lock-out of the addressed portion while allowing subsequent commands to simultaneously access other addressed areas of the memory.
U.S. Pat. No. 3,735,360 for "High Speed Buffer Operation in a Multi-Processing System" issued May 22, 1973 to David Anderson et al describes a system in which address information is broadcast from each processor to the others for the purpose of invalidating data in the individual memories of the processor, and for insuring that the data obtained from a processor from the shared storage is the most current value.
The above-referenced patents do not disclose the address-based locking and priority circuits of the present invention that are used to lock-out only a specified portion of the shared memory while allowing simultaneous access to the other areas.